EDIF Input File Definition An EDIF version 2 0 0 netlist file (with the extension (.edf), generated by any standard EDIF netlist writer. The Quartus II software also supports EDIF Input files with the extensions (.edif) or (.edn).When you compile an EDIF Input File, the Compiler uses one or more Library Mapping Files (.lmf) to map cells in an EDIF Input File to corresponding Quartus II logic functions, including Library of Parameterized Modules (LPM) functions, as well as to user-defined functions.All logic functions in an EDIF Input File must be mapped to the Quartus II software logic functions in a Library Mapping File (.lmf). If you wish to use a function that is not mapped in a Altera-provided LMF, you must create a customized LMF. You can map EDIF cells to Altera-provided functions or to any design file created with the Quartus II software.The Compiler processes EDIF Input Files automatically, generating a Compiler Netlist Extractor (.cnf) file for every cell in an EDIF Input File. You can also specify EDIF Input settings to help the Compiler interpret EDIF Input Files by specifying optional LMFs and non-default VCC and GND signal names.A single EDIF Input File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project.The Quartus II software automatically creates a Block Symbol File (.bsf) that represents an EDIF Input File when you open the file in the Text Editor and create the default symbol for the current file. This symbol and the logic it represents can be incorporated into a Block Design File (.bdf).You can also use EDIF Input File logic in an AHDL Text Design File (.tdf) by including a Function Prototype and inserting an instance of the function into the TDF.You can import some resource assignments into the Quartus II software with the following EDIF property constructs:Construct:Type of Assignment:chip_pin_lcChip, pin, logic cellcliquecliquelogic_optionLogic optionAs an alternative, you can use the Assignment Editor in the Quartus II software to make all types of assignments--including location and device assignments--for the logic in the EDIF Input File.To properly convert an EDIF Input File, EDIF constructs must have the following values:Construct:Value:edifLevel0keywordLevel0viewTypeNETLISTcellTypeGENERICThe file name may be truncated to 8 characters. If you truncate the file name, you must then either rename the file with its previous longer file name from within the Quartus II software, or edit the file to change any instances of the file name to the new, truncated name. To rename the file from within the Quartus II software, open the file with the truncated name in the Text Editor and save it to its previous longer file name. However, if your file transfer software inserts characters into the truncated name that are not legal Quartus II software name characters, you may need to first rename the file from the DOS command line before you can open it in the Text Editor.

AMD/XILINX vivado 问题汇总 问题 一：1.WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.2.INFO: [Labtools 27-1434] Device xc7k410t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.3.WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. You must manually launch hw_server4.with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.5.To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].6.WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7k410t_0 and the probes file D:/Vivado/xc7k410t-2ffg900/ddr_slave_410t_20150527_1/ddr_slave_410t_20150527_1.runs/impl_1/debug_nets.ltx.7.The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).8.Resolution:9.1. Reprogram device with the correct programming file and associated probes file OR10.2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.复制代码大概是说设计里没有ILA core，但是debug文件里有ILA core，而且debug probes窗口下什么也没有。但是，我综合后明明插入了debug core呀，而且在约束文件里也自动生成了相关信息，查看schematic，也添加了debug相关的两个元件，为毛program时就是看不到呢？不知道有没有人遇到过类似的情况，求指点，万分感谢！解决：1： VIO 和 ILA 的CLK 有问题。2： 我查的Xilinx的论坛，貌似也这么说，说是要用free running clock，但我也没弄明白什么样的叫free running clock。我用的就是那些寄存器本来的时钟，如果换个时钟的话，怎么能保证采样不会出问题呢？还是不太明白，能否详细指教？谢谢啦！       所谓的free running clock就是上电就跑的时钟，而不是依赖某些条件才有的。补充一点，FREE CLOCK的确是要求上电无条件运行的时钟。有一次我碰到一种情况。用MMCM或者PLL输出的时钟作为采样时钟，但是如果MMCM或者PLL这个输入并不是上电就来的话，而是等FPGA程序运行了之后时钟输入才来，那么下载程序之后还是在ILA调试界面看不到任何信号。把MMCM或者PLL的输入时钟改为晶振的时钟，那么就可以正常使用ILA了。这是我的个人感觉，没有经过大量验证，所以希望大家多多指教。补充一点，FREE CLOCK的确是要求上电无条件运行的时钟。        其实不用FREE CLOCK也没问题。比方用ZYNQ PS产生的CLK也可以。上电后做PS初始化，再把需要的寄存器设定一下，然后更新一下DEVICE，就可以找到ILA了。3 ： 这个问题我遇到过，其实第一种情况是你的时钟信号可能没加入成功（比如外部输出时钟信号没进来或者幅度太小，内部时钟可能没有lock）；第二种情况是，你输入到ila核的时钟频率不合适。其实，ila就是个采样你需要的查看的信号的始终，因此最好是直接用外部始终的mmcm生成大于你需要采集信号的最高频率来采样（具体多大频率，看你采样点数的需求和你信号的频率了）。4： 这个问题是时钟引起的。当bit file program完成之后，fpga/vivado会自动检测ila的clock是否存在，如果不存在(在本例中是pll/mmcm没有lock)，它就会report 这个warning。这个时候我们只要让时钟工作起来，refresh一下device，ila就会启动--ila的窗口就会出来了。5 ： 你试试直接用外部输入的时钟（可经过时钟buf）作为ila的clk，不要用其它模块产生的时钟。问题 二：我在vivado下进行调试，调用了ILA IP Core。如果ila采用晶振输入作为clk时（也即全局时钟），在顶层RTL级，可以看到ila的数据和时钟都连上了。Debug时也能在Hardware下看到XADC和ILA。但如果ila的clk，采用逻辑计数办法分频后的时钟信号、或者采用clock wizard倍频后的时钟信号。在顶层RTL下看ILA的clk并没有和上述时钟源连接上。此时将bit流下载后Debug，也只能看到XADC而看不到ILA核。  想知道使用ILA时，ila的clk的输入源是不是有什么特殊限制？解决：1 ： 难道是：（Xilinx PG172）The clk input port is the clock used by the ILA core to register the probe values. For best results, it should be the same clock signal that is synchronous to the design logic that is attached to the probe ports of the ILA core.    2 ： 首先确保你的分频结果是有效的。然后，如果你非要用分频结果的话，过一个bufg试试。// BUFG: 全局时钟缓存（Global Clock Buffer），只能以内部信号驱动  // Xilinx HDL库向导版本，ISE 9.1  BUFG BUFG_inst (  .O(O), //时钟缓存输出信号  .I(I) // /时钟缓存输入信号  );  // 结束BUFG_ins模块的例化过程